Do Variables Create Registers Inside The Process

One question that I've debated many times over the years is whether information technology'due south OK to use variables for registers in VHDL. Information technology'south safe to say that newbies are more probable to practise it than experienced VHDL designers. Merely is there whatsoever merit to that, or is information technology just a matter of preference?

In this blog postal service, I will effort to shed some calorie-free on the upshot so that you tin make an informed decision about using this design exercise.

Beginning of all, let me explicate what I hateful by using a variable as a annals.

If you read a variable in a VHDL process before you write to it, the synthesis tool will have to implement it using concrete storage. That's because its value has to be stored somewhere until the next time the process wakes upward. In FPGAs, that means either registers (flip-flops) or retentivity (block RAM).

The code below shows an example process where my_var is not a register. The logic doesn't rely on whatsoever previous value of the variable. We give it a default value of '0' as presently every bit nosotros enter the process.

procedure(clk)   variable my_var : std_logic; begin   if rising_edge(clk) then          my_var := '0';      if some_condition and then       my_var := some_value;     terminate if;      my_signal <= my_var;    terminate if; end process;

If nosotros comment out the default assignment to my_var, as shown in the example below, it becomes a register. That's because if some_condition is faux, my_signal gets whatever value my_var had the last fourth dimension the procedure completed. You are telling the synthesis tool to think the value of my_var over time, and the only manner to practice that is past using a register.

process(clk)   variable my_var : std_logic; begin   if rising_edge(clk) so          -- my_var := '0';      if some_condition then       my_var := some_value;     stop if;      my_signal <= my_var;    terminate if; cease process;

It'southward perfectly legal to use variables like that in VHDL. Likewise, the FPGA tools won't accept any trouble implementing it most of the time. Still, it'south a pattern practise that's frowned upon by many FPGA engineers. Some companies fifty-fifty prohibit such use of variables through their coding standards. Allow'southward have a look at an example and examine the pros and cons of using variables over signals.

Example using a variable to infer block RAM

In this example, I've created a VHDL process for inferring a dual-port RAM. The width and depth friction match a configuration of the Xilinx RAMB36E1 primitive, equally shown on page 30 of the 7 Series FPGAs Memory Resources user guide. The code below shows the VHDL procedure. Nosotros shop the values in the ram_v object, which is a regular variable.

DUAL_PORT_RAM : process(clk)   type ram_type is array (0 to ii**10 - 1) of std_logic_vector(35 downto 0);   variable ram_v : ram_type; begin   if rising_edge(clk) and then      data_out <= ram_v(addr_out);     ram_v(addr_in) := data_in;        end if; end procedure;

When we synthesize the code in Xilinx Vivado, we see that it has indeed implemented ram_v in block RAM. Beneath is an extract from the synthesis log, showing the variable'south name mapped to a RAMB36 primitive.

Block RAM: Preliminary Mapping	Report (run into note beneath) +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth 10 Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |  +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |bram        | ram_v_reg  | i K x 36(READ_FIRST)   | Westward |   | 1 1000 x 36(WRITE_FIRST)  |   | R | Port A and B     | 0      | ane      |  +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

Variables used for limiting the scope

A possible reward of using a variable is that its scope is limited to within the process. Forth with the variable, we tin can also place the blazon declaration of the array inside of the procedure. Limiting the scope of data objects is mostly considered to be a skilful coding practice. Keeping all the constructs that "belong" to the process within it helps to refine the process as a carve up design unit.

At that place are ways of creating limited scopes for signals besides, for case, by using the VHDL block statement. But equally y'all can see from the example below, it adds more than code lines and another indentation level to your VHDL file. I accept to give a small victory to variables when information technology comes to encapsulation.

RAM_BLOCK : block    type ram_type is assortment (0 to two**x - i) of std_logic_vector(35 downto 0);   signal ram : ram_type;  brainstorm    DUAL_PORT_RAM : process(clk)   begin     if rising_edge(clk) and then        data_out <= ram(addr_out);       ram(addr_in) <= data_in;            end if;   end process;  end cake RAM_BLOCK;

Line ordering matters with variables

A thing to be aware of when using variables is that the ordering of the lines affair. If we swap lines 7 and 8 in the original DUAL_PORT_RAM process, it's broken. That'southward not the case if nosotros swap lines 12 and 13 in the lawmaking in a higher place. With signals, simply which enclosure they are within matters, while with variables, the correct ordering of code lines is crucial.

Refer to my earlier blog post to empathize the general difference between signals and variables:
How a signal is different from a variable in VHDL

That'southward one of the main objections many VHDL designers have confronting variables used for registers. Some engineers are accustomed to reading the lawmaking within an enclosure, similar an if-statement, every bit parallel events. Past using both variables and signals interchangeably, it becomes harder to follow the plan flow. The code becomes less readable because your mind has to embrace 2 constructs with different sets of rules, describing the same affair.

Of course, the arguments nigh readability is a subjective one. Furthermore, if you lot expect only signals to describe registers, y'all may be more inclined to overlook a variable that does the aforementioned. Simply if you apply variables for that regularly, it may not exist that large an issue for you.

Viewing variables in the ModelSim waveform

When using variables for data storage, you may want to runway the value over time in the simulator. Nearly simulators treat variables different from signals in many means. In ModelSim, they are not immediately accessible from the Objects window. It's something to be aware of, but it's a minor trouble.

The video higher up shows how y'all can add together a variable to the waveform in ModelSim. Bring up the Locals window by choosing View→Locals from the principal card. Select the process that contains the variable, and it will appear under Locals. Right-click the variable and add select Add Wave, only as you would with a signal.

Final thoughts

Before writing this article, I posted a question in my private Facebook grouping to see what other FPGA engineers had to say almost using variables for storage. Equally I expected, nearly dislike using variables in this style in RTL modules. The consensus is that they are confusing to work with when they presume the same role as signals: to act as registers.

One user wrote that there'south a higher adventure of creating latches with variables than signals. I've heard that argument before, and I tried to construct an example to demonstrate the problem, but I couldn't. I wasn't able to find any situations where a variable causes a latch while a signal doesn't. Of course, that doesn't hateful that it can't happen. But we will have to get out that statement unconfirmed at the moment.

Leave a comment if yous have such an example!

Finally, a user whose outset proper name is Ray sums up nicely what I retrieve is the nearly significate statement against variables. He says:

My problem with this is that you are now relying on the synthesis tool to do "the right matter" rather than simply writing code that makes it exercise the right thing.

I would only utilize variables in processes that are implementing some combinatorial logic. Then I'd register that output in a split up clocked procedure with its own reset.

And I accept to concord on that. It's ameliorate to exist explicit in VHDL. If you want a register, information technology'due south safest to utilize a signal.

I'm from Norway, but I alive in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defence force industry. I earned my principal's degree in informatics at the Academy of Oslo.